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Die shrink
The term die shrink (sometimes optical shrink or process shrink) refers to a simple semiconductor scaling of semiconductor devices, mainly transistors. The act of shrinking a die is to create a somewhat identical circuitry using a more advanced fabrication process, usually involving an advance of lithographic node. This reduces overall costs of a chip company, as the absence of major architectural changes to the processor lowers research and development costs, while at the same time allowing more processor dies to be manufactured on the same piece of silicon wafer, resulting in less cost per product sold.
== Details ==
Die shrinks are the key to improving price/performance at semiconductor companies such as Intel, AMD (including the former ATI), NVIDIA, and Samsung. Examples in the 2000s include the codenamed Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) and Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS), the codenamed Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI), and various generations of GPUs from both ATI and NVIDIA. In January 2010, Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture.
Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices. Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps, and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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